DMOS Full-Bridge Motor Driver
Features and Benefits
▪ Low RDS(on) outputs▪ Overcurrent protection
▪ Motor lead short-to-supply protection▪ Short-to-ground protection▪ Sleep function▪ Synchronous rectification▪ Diagnostic output
▪ Internal undervoltage lockout (UVLO)▪ Crossover-current protection
Description
Designed for PWM (pulse width modulated) control of DC
motors, the A3950 is capable of peak output currents to ±2.8 A and operating voltages to 36 V.
PHASE and ENABLE input terminals are provided for use in controlling the speed and direction of a DC motor with externally applied PWM control signals. Internal synchronous rectification control circuitry is provided to lower power dissipation during PWM operation.
Internal circuit protection includes motor lead short-to-supply / short-to-ground, thermal shutdown with hysteresis, undervoltage monitoring of VBB and VCP, and crossover-current protection.
Package EU, 16 pin QFNwith Exposed Thermal Pad
Packages:
Package LP, 16 pin TSSOP with Exposed Thermal Pad
The A3950 is supplied in a thin profile (<1.2 mm overall height) 16 pin TSSOP package (LP), and a very thin (0.75 mm nominal height) QFN package. Both packages provide an exposed pad for enhanced thermal dissipation, and are lead (Pb) free with 100% matte tin leadframe plating.
Approximate Scale 1:1
Typical Application Diagrams
VBB0.1 μF50 VNFAULTGNDCP2100 μF50 VNCVREGVCP0.1 μF50 V0.22 μF25 V0.22 μF25 VVBBNFAULTMODEVDD5 kΩPHASEGNDSLEEPENABLEVREGVCPVDD5 kΩMODEPHASEGND SLEEPENABLEOUTASENSEA3950EU PackageSENSEOUTACP1OUTB0.1 μF50 VA3950LP PackageGNDCP2 CP1OUTBVBB0.1 μF50 V100 μF50 V0.1 μF50 VVBB0.1 μF50 VNCPackage EUPackage LP
A3950DS, Rev. 6
A3950DMOS Full-Bridge Motor Driver
Selection Guide
Part Number
A3950SLPTR-TA3950SEUTR-T
Packing
13 in. reel, 4000 pieces / reel7 in. reel, 1500 pieces / reel
Package
16 pin TSSOP with exposed thermal pad16 pin QFN with exposed thermal pad
Absolute Maximum Ratings
Characteristic
Load Supply VoltageOutput CurrentSense VoltageVBB to OUTxOUTx to SENSELogic Input Voltage
Operating Ambient TemperatureMaximum Junction TemperatureStorage Temperature
VINTATJ(max)Tstg
Range S
SymbolVBBIOUTVSENSE
Notes
Rating362.8±5003636–0.3 to 7–20 to 85150–40 to 125
UnitsVAmVVVVºCºCºC
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000www.allegromicro.com
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A3950DMOS Full-Bridge Motor Driver
Functional Block Diagram
0.1 μFCP1CP2ChargePumpVCP0.1 μFVREG0.22 μF25 VMODELow-SideGate SupplyBiasSupplyVBBLoad Supply0.1 μF100 μFPHASEControl LogicVDDENABLE5 kΩSLEEP5 kΩNFAULTUVLOSTBSTGTSD WarningVBBOUTAOUTBSENSEOUTAOUTBSENSEMotor LeadProtection GNDPadGNDTerminal List TableNameNFAULTMODEPHASEGNDSLEEPENABLEOUTASENSEVBBOUTBCP1CP2VCPVREGNCPad
NumberEU151612, 12346789101113145–
LP1234,1356789101112141516–
Description
Fault output, open drainLogic input
Logic input for direction controlGroundLogic inputLogic input
DMOS full-bridge output APower return
Load supply voltage
DMOS full-bridge output B
Charge pump capacitor terminalCharge pump capacitor terminalReservoir capacitor terminalRegulator decoupling terminalNo connection
Exposed pad for thermal dissipation connect to GND pins
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000www.allegromicro.com
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A3950DMOS Full-Bridge Motor Driver
ELECTRICAL CHARACTERISTICS at TJ = 25°C, VBB = 8 to 36 V, unless noted otherwise
CharacteristicsSymbolTest ConditionsfPWM < 50 kHz Motor Supply CurrentIBBCharge pump on, outputs disabled
Sleep modeVIHPHASE, ENABLE, MODE Input
Voltage VIL
VIH
SLEEP Input Voltage
VILIIHVIN = 2.0 VPHASE, MODE Input Current1
IILVIN = 0.8 VVIN = 2.0 VIIH
ENABLE Input Current
IILVIN = 0.8 VIIHVIN = 2.7 V
SLEEP Input Current
IILVIN = 0.8 VNFAULT Output VoltageVOLIsink = 1.0 mAInput Hysteresis, except SLEEPVIHys
Source driver, IOUT = -2.8 A, TJ=25°CSource driver, IOUT = -2.8 A, TJ=125°COutput On ResistanceRDS(on)
Sink driver, IOUT = 2.8 A, TJ=25°CSink driver, IOUT = 2.8 A, TJ=125°CSource diode, If = –2.8 A
Body Diode Forward Voltage1Vf
Sink diode, If = 2.8 APWM, change to source or sink ONPropagation Delay Timetpd
PWM, change to source or sink OFFCrossover DelaytCODProtection CircuitryUVLO ThresholdVUVVBB increasingUVLO HysteresisVUVHys
2Overcurrent ThresholdIOCP
Overcurrent Protection PeriodtOCPThermal Warning TemperatureTJWTemperature increasingThermal Warning HysteresisTJWHysRecovery = TJW – TJWHysThermal Shutdown TemperatureTJTSDTemperature increasingThermal Shutdown HysteresisTJTSDHysRecovery = TJTSD – TJTSDHys
2Overcurrent protection is tested at 25°C in a restricted range and guaranteed by characterization.
Min.Typ.Max.Units–68.5mA–34.5mA––10μA2.0––V––0.8V2.7––V––0.8V–<1.020μA–20<–2.020μA–40100μA–1640μA–2750μA–<110μA––0.4V100150250mV–0.350.48Ω–0.550.8Ω–0.30.43Ω–0.450.7Ω––1.4V––1.4V–600–ns–100–ns–500–ns––3–––––
6.5250–1.21601517515
––––––––
VmVAms°C°C°C°C
1For input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin.THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information
Characteristic
Symbol
Test Conditions*
Preliminary: EU package, 4-layer PCB based on JEDEC standard
Package Thermal Resistance
RθJA
LP package, 4-layer PCB based on JEDEC standard
LP package, 2-layer PCB with 3.8 in.2 copper both sides, connected by thermal vias
*Additional thermal data available on the Allegro Web site.
Value303443
UnitsºC/WºC/WºC/W
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000www.allegromicro.com
4
A3950DMOS Full-Bridge Motor Driver
Timing Diagram: PWM Control
SLEEPENABLEPHASEMODE
VBB
VOUTA
0
VBB
VOUTB
0
IOUTX
0
A123456789VBB156OutA324OutBOutA8VBB7OutB9ACharge pump and VREG power-on delay (≈200 μs)Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000www.allegromicro.com
5
A3950DMOS Full-Bridge Motor Driver
Timing Diagram: Overcurrent Control
VOUTA
VOUTBHigh-ZIPEAKIOCPIOUTx
ENABLE,Sourceor SinkBLANK
Charge Pump
Counter
tBLANKtOCPNFAULT
Motor lead short condition
Normal dc
motor capacitance
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000www.allegromicro.com
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A3950DMOS Full-Bridge Motor Driver
Functional Description
Device Operation. The A3950 is designed to operate one DC motor. The output drivers are all low RDS(on) N-channel DMOS drivers that feature internal synchronous rectification to reduce power dissipation. PHASE and ENABLE inputs allow two-wire control with an additional MODE pin for the brake function. A low current Sleep mode is provided to minimize power consump-tion when the driver is disabled. In addition, the driver also has built-in protection from short-to-ground, short-to-battery, and shorted load events.
Logic Inputs. If logic inputs are pulled up to VDD , it is good practice to use a high value pull-up resistor in order to limit cur-rent to the logic inputs should an overvoltage event occur. Logic inputs include: SLEEP, MODE, PHASE, and ENABLE. The voltage on any logic input cannot exceed the specified maximum of 7 V.
VREG. This supply voltage is used to run the sink-side DMOS outputs. VREG is internally monitored and in the case of a fault condition, the outputs of the device are disabled. The VREG pin should be decoupled with a 0.22 μF capacitor to ground.Charge Pump. The charge pump is used to generate a sup-ply above VBB to drive the source-side DMOS gates. A 0.1 μF ceramic monolithic capacitor should be connected between CP1 and CP2 for pumping purposes. A 0.1 μF ceramic monolithic capacitor should be connected between VCP and VBB to act as a reservoir to run the high-side DMOS devices. The VCP voltage level is internally monitored and, in the case of a fault condition, the outputs of the device are disabled.
Shutdown. In the event of a fault due to excessive junction temperature, or low voltage on VCP or VREG, the outputs of
Control Logic Table1
Pin
PHASE10X10X
ENABLE
11000X
MODEXX100X
SLEEP111110
OUTAHLLLHZ
OUTBLHLHLZ
ForwardReverse
Brake (slow decay)
Fast Decay Synchronous Rectification2Fast Decay Synchronous Rectification2Sleep Mode
Function
the device are disabled until the fault condition is removed. At power-on the UVLO circuit disables the drivers.
Sleep Mode. Control input SLEEP is used to minimize power consumption when the A3950 is not in use. This disables much of the internal circuitry, including the regulator and charge pump. A logic low setting puts the device into Sleep mode, and a logic high setting allows normal operation. After coming out of Sleep mode, provide a 1 ms interval before applying PWM signals, to allow the charge pump to stabilize.
MODE. Control input MODE is used to toggle between fast
decay mode and slow decay mode. A logic high puts the device in slow decay mode. Synchronous rectification is always enabled.Braking. The braking function is implemented by driving the device in slow decay mode via the MODE setting and applying an enable chop command. Because it is possible to drive current in both directions through the DMOS switches, this configuration effectively shorts out the motor generated BEMF as long as the ENABLE chop mode is asserted. The maximum current can be approximated by VBEMF/RL. Care should be taken to insure that the maximum ratings of the device are not exceeded in worse case braking situations: high speed and high-inertia loads.Diagnostic Output. The NFAULT pin signals a problem with the chip via an open drain output. A motor fault, undervoltage condition, or TJ > 160°C will drive the pin active low. This output is not valid when SLEEP puts the device into minimum power dissipation mode.
TSD. Two die temperature monitors are integrated on the chip. As die temperature increases towards the maximum, a thermal warning signal will be triggered at 160°C. This fault drives the
1X indicates “don’t care,” Z indicates high impedance.
2To prevent reversal of current during fast decay synchronous rectification, outputs go to the high impedance state as the current approaches 0 A.
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000www.allegromicro.com
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A3950DMOS Full-Bridge Motor Driver
NFAULT low, but does not disable the operation of the chip. If the die temperature increases further, to approximately 175°C, the full-bridge outputs will be disabled until the internal temperature falls below a hysteresis of 15°C.
Overcurrent Protection. Referring to the figures below, the voltage on the output pins relative to supply are monitored to ensure that the motor lead is not shorted to supply or ground.
If a short is detected, the full-bridge outputs are turned off, flag NFAULT is driven low, and a 1.2 ms fault timer is started.After this 1.2 ms period, tOCP , the device will then be allowed to follow the input commands and another turn-on is attempted. If there is still a fault condition, the cycle repeats. If, after tOCP expires, it is determined that the short condition is not present, the NFAULT pin is released and normal operation resumes.
2 μs / div.2 A / div.ISHORT
Fault assertedNFAULT
Shorted load condition, output current waveform is shown along with the NFAULT output.
TOCP = 1.2 ms200 μs / div.2 A / div.ISHORT
Fault assertedNFAULT
Shorted load condition illustrating repetitive cycles with a 1.2 ms delay.
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000www.allegromicro.com
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A3950DMOS Full-Bridge Motor Driver
Applications Information
Power Dissipation. First order approximation of power dissipation in the A3950 can be calculated by first examining the power dissipation in the full-bridge during each of the operation modes. The A3950 features synchronous rectifica-tion, a feature that effectively shorts out the body diode by turning on the low RDS(on) DMOS driver during the decay cycle. This significantly reduces power dissipation in the full-bridge. In order to prevent shoot-through, where both
source and sink driver are on at the same time, the A3950 implements a 500 ns typical crossover delay time. For this period, the body diode in the decay current path conducts the current until the DMOS driver turns on. This does affect power dissipation and should be considered in high current, high ambient temperature applications. In addition, motor parameters and switching losses can add power dissipation that could affect critical applications.
Drive Current. This current path is through source DMOS driver, motor winding, and sink DMOS driver. Power dissi-pation is I2R loses in one source and one sink DMOS driver, as shown in the following equation:
VBBPD=I2(RDS(on)Source+RDS(on)Sink)132 (1)
Fast Decay with Synchronous Rectification. This decay mode is equivalent to a phase change where the oppo-site drivers are switched on. When in fast decay, the motor current is not allowed to go negative (direction change). Instead, as the current approaches zero, the drivers turn off. The power calculation is the same as the drive current calcu-lation, equation 1:
Slow Decay SR (Brake Mode). In this decay mode, both sink drivers turn on, allowing the current to circulate through the sink drivers and the load. Power dissipation is I2R loses in the two sink DMOS drivers:
1Drive current2Fast decay with synchronous rectification (reverse)3Slow decay with synchronous rectification (brake)Figure 1. Current Decay Patterns
PD=I2(2×RDS(on)Sink) (2)
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000www.allegromicro.com
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A3950DMOS Full-Bridge Motor Driver
SENSE Pin. A low value resistor can be placed between the SENSE pin and ground for current sensing purposes. To mini-mize ground-trace IR drops in sensing the output current level, the current sensing resistor should have an independent ground return to the star ground point. This trace should be as short as possible. For low value sense resistors, the IR drops in the PCB can be significant, and should be taken into account. When selecting a value for the sense resistor be sure not to exceed the maximum voltage on the SENSE pin of ±500 mV.Ground. A star ground should be located as close to the A3950 as possible. The copper ground plane directly under the exposed thermal pad makes a good location for the star ground point. The exposed pad can be connected to ground for this purpose.
Layout. The printed circuit board should use a heavy ground-plane. For optimum electrical and thermal performance, the A3950 must be soldered directly onto the board. On the under-side of the A3950 package is an exposed pad, which provides a path for enhanced thermal dissipation. The thermal pad should be soldered directly to an exposed surface on the PCB. Thermal vias are used to transfer heat to other layers of the PCB.
The load supply pin, VBB, should be decoupled with an elec-trolytic capacitor (typically 100 μF) in parallel with a ceramic capacitor placed as close as possible to the device. The ceramic capacitors between VCP and VBB, connected to VREG, and between CP1 and CP2, should be as close to the pins of the device as possible, in order to minimize lead inductance.
VBBC1NFAULTMODEVREGC1C2VBBVCPC2U1GNDC3CVBB1PHASEGNDSLEEPENABLECVBB1GNDCP2CP1OUTBC3A3950EU PackagePADSENSEOUTACVBB2GNDCVBB2OUTAOUTBEU package shown
VBBNCAllegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000www.allegromicro.com
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A3950DMOS Full-Bridge Motor Driver
EU Package, 16 Pin QFN with Exposed Thermal Pad
0.354.00 ±0.15161.15124.00 ±0.15A122.153.80160.652.153.8017XD0.08C0.30 ±0.050.65SEATINGPLANE0.75 ±0.05CCPCB Layout Reference ViewFor Reference Only
(reference JEDEC MO-220WGGC)Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shownATerminal #1 mark area
BExposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion)
0.40 ±0.10B21162.152.15CReference land pattern layout (reference IPC7351 QFN65P400X400X80-17BM)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)DCoplanarity includes exposed thermal pad and terminals
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000www.allegromicro.com
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A3950DMOS Full-Bridge Motor DriverLP Package, 16 Pin TSSOP with Exposed Thermal Pad
5.00 ±0.10164° ±4+0.050.15–0.06
1.70160.450.65B3.00A4.40 ±0.10 6.40 ±0.20 0.60 ±0.15(1.00)3.006.10123.000.25SEATINGPLANE0.651.20 MAX0.15 MAXCSEATING PLANEGAUGE PLANE123.00CPCB Layout Reference View
16X0.10C+0.050.25–0.06For Reference Only
(reference JEDEC MO-153 ABT)Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shownATerminal #1 mark area
BExposed thermal pad (bottom surface)
CReference land pattern layout (reference IPC7351 SOP65P640X110-17M); All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
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