MOTOROLASEMICONDUCTOR TECHNICAL DATAMC14042BQuad Transparent LatchThe MC14042B Quad Transparent Latch is constructed with MOSP–channel and N–channel enhancement mode devices in a singlemonolithic structure. Each latch has a separate data input, but all fourlatches share a common clock. The clock polarity (high or low) used tostrobe data through the latches can be reversed using the polarity input.Information present at the data input is transferred to outputs Q and Q duringthe clock level which is determined by the polarity input. When the polarityinput is in the logic “0” state, data is transferred during the low clock level,and when the polarity input is in the logic “1” state the transfer occurs duringthe high clock level.•••••••Buffered Data InputsCommon ClockClock Polarity ControlQ and Q OutputsDouble Diode Input ProtectionSupply Voltage Range = 3.0 Vdc to 1 8 VdcCapable of Driving Two Low–power TTL Loads or One Low–powerSchottky TTL Load Over the Rated Temperature RangeL SUFFIXCERAMICCASE 620P SUFFIXPLASTICCASE 648D SUFFIXSOICCASE 751BORDERING INFORMATIONMC14XXXBCPMC14XXXBCLMC14XXXBDPlasticCeramicSOICTA = – 55° to 125°C for all packages.MAXIMUM RATINGS* (Voltages Referenced to VSS)SymbolParameterVDDVin, Voutlin, loutPDTstgDC Supply VoltageValueUnitVVPIN ASSIGNMENTQ3Q0Q0D0CLOCKPOLARITYD1VSS12345678161514131211109VDDQ3D3D2Q2Q2Q1Q1– 0.5 to + 18.0Input or Output Voltage (DC or Transient)Input or Output Current (DC or Transient),per PinPower Dissipation, per Package†Storage Temperature– 0.5 to VDD + 0.5± 10500mAmW_C– 65 to + 150TLLead Temperature (8–Second Soldering)260_C*Maximum Ratings are those values beyond which damage to the device may occur.†Temperature Derating:Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_CCeramic “L” Packages: – 12 mW/_C From 100_C To 125_CLOGIC DIAGRAM56D17LATCH2D04LATCH123Q0ClockQ00110TRUTH TABLEPolarity0011QDataLatchDataLatchCLOCKPOLARITY109Q1Q1D213LATCH31112Q2Q2VDD = PIN 16VSS = PIN 8D314LATCH4115Q3Q3REV 31/94©MC14042B Motorola, Inc. 1995156MOTOROLA CMOS LOGIC DATAELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)CharacteristicSymbolVOLVDDVdc5.010155.010155.010155.010155.05.010155.0101515—5.010155.01015Min———– 55_C25_C125_CMaxMin———Typ #000MaxMin———MaxUnitVdcOutput VoltageVin = VDD or 0 “0” Level0.050.050.05———0.050.050.05———0.050.050.05———“1” LevelVin = 0 or VDDVOH4.959.9514.95———4.959.9514.95———5.010154.959.9514.95———VdcInput Voltage“0” Level(VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc)“1” Level(VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc)VILVdc1.53.04.0——————————2.254.506.752.755.508.251.53.04.0——————————1.53.04.0——————————VIHVdc3.57.0113.57.0113.57.011Output Drive Current(VOH = 2.5 Vdc) (VOH = 4.6 Vdc)(VOH = 9.5 Vdc)(VOH = 13.5 Vdc)(VOL = 0.4 Vdc) (VOL = 0.5 Vdc)(VOL = 1.5 Vdc)SourceIOHmAdc– 3.0– 0.64– 1.6– 4.20.641.64.2—————– 2.4– 0.51– 1.3– 3.40.511.33.4—————– 4.2– 0.88– 2.25– 8.80.882.258.8– 1.7– 0.36– 0.9– 2.40.360.92.4—————SinkIOLmAdcInput CurrentInput Capacitance(Vin = 0)Iin± 0.1—1.02.04.0±0.000015.00.0020.0040.006± 0.17.51.02.04.0± 1.0—3060120µAdcpFµAdcCinQuiescent Current(Per Package)IDDTotal Supply Current**†(Dynamic plus Quiescent,Per Package) (CL = 50 pF on all outputs all buffers switching)ITIT = (1.0 µA/kHz) f + IDDIT = (2.0 µA/kHz) f + IDDIT = (3.0 µA/kHz) f + IDDµAdc#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.**The formulas given are for the typical characteristics only at 25_C.†To calculate total supply current at loads other than 50 pF:IT(CL) = IT(50 pF) + (CL – 50) Vfkwhere: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.004.This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However,precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedancecircuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs mustbe left open.MOTOROLA CMOS LOGIC DATAMC14042B157SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)CharacteristicOutput Rise and Fall TimetTLH, tTHL = (1.5 ns/pF) CL + 25 nstTLH, tTHL = (0.75 ns/pF) CL + 12.5 nstTLH, tTHL = (0.55 ns/pF) CL + 9.5 nsPropagation Delay Time, D to Q, QtPLH, tPHL = (1.7 ns/pF) CL + 135 nstPLH, tPHL = (0.66 ns/pF) CL + 57 nstPLH, tPHL = (0.5 ns/pF) CL + 35 nsPropagation Delay Time, Clock to Q, QtPLH, tPHL = (1.7 ns/pF) CL + 135 nstPLH, tPHL = (0.66 ns/pF) CL + 57 nstPLH, tPHL = (0.5 ns/pF) CL + 35 nsClock Pulse WidthSymboltTLH,tTHLVDD5.010155.010155.010155.010155.010155.010155.01015Min—————————Typ #1005040220906022090601505040———Max20010080440180120440180120———UnitnstPLH,tPHLnotPLH,tPHLnstWHns30010080———Clock Pulse Rise and Fall TimetTLH,tTHLµs155.04.0——————Hold Timethns1005040503025502520000Setup Timetsuns*The formulas given are for the typical characteristics only at 25_C.#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.1656PULSEGENERATOR 1471314VDD20 ns1f20 ns90%50%DATA INPUTtPLH90%Q OUTPUT10%tTLHQ OUTPUTtPHL90%10%tTHL50%tTLH10%tPHL50%tTHLQ0Q0Q1Q1Q2Q2Q3Q3231091112115CLOCKPOLARITYD0D1D2D38For Power Dissipation test, each outputis loaded with capacitance CL.VSSFigure 1. AC and Power Dissipation Test Circuit and Timing Diagram(Data to Output)MC14042B158MOTOROLA CMOS LOGIC DATAVDD16PULSEGENERATOR 1PULSEGENERATOR 256471314NOTE:CL connected to output under test.CLOCKPOLARITYD0D1D2D38Q0Q0Q1Q1Q2Q2Q3Q3231091112115VSS20* ns90%20 ns50%CLOCK INPUTP.G. 110%20 ns90%50%DATA INPUTP.G. 2Q OUTPUT90%50%10%*Input clock rise time is 20 ns except for maximum rise time test.tsutPLHthtWHFigure 2. AC Test Circuit and Timing Diagram(Clock to Output)MOTOROLA CMOS LOGIC DATAMC14042B159OUTLINE DIMENSIONSL SUFFIXCERAMIC DIP PACKAGECASE 620–10ISSUE V–A–169NOTES:1.DIMENSIONING AND TOLERANCING PERANSI Y14.5M, 1982.2.CONTROLLING DIMENSION: INCH.3.DIMENSION L TO CENTER OF LEAD WHENFORMED PARALLEL.4.DIMENSION F MAY NARROW TO 0.76 (0.030)WHERE THE LEAD ENTERS THE CERAMICBODY.DIMABCDEFGHKLMNINCHESMINMAX0.7500.7850.2400.295–––0.2000.0150.0200.050 BSC0.0550.0650.100 BSC0.0080.0150.1250.1700.300 BSC0 _15 _0.0200.040MILLIMETERSMINMAX19.0519.936.107.49–––5.080.390.501.27 BSC1.401.652.54 BSC0.210.383.184.317.62 BSC0 _15 _0.511.01–B–18CL–T–SEATINGPLANENEFDG16 PLKMJ16 PL0.25 (0.010)MMTBS0.25 (0.010)TASP SUFFIXPLASTIC DIP PACKAGECASE 648–08ISSUE R–A–169NOTES:1.DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2.CONTROLLING DIMENSION: INCH.3.DIMENSION L TO CENTER OF LEADS WHENFORMED PARALLEL.4.DIMENSION B DOES NOT INCLUDE MOLD FLASH.5.ROUNDED CORNERS OPTIONAL.DIMABCDFGHJKLMSINCHESMINMAX0.7400.7700.2500.2700.1450.1750.0150.0210.0400.700.100 BSC0.050 BSC0.0080.0150.1100.1300.2950.3050 _10 _0.0200.040MILLIMETERSMINMAX18.8019.556.356.853.694.440.390.531.021.772.54 BSC1.27 BSC0.210.382.803.307.507.740 _10 _0.511.01B18FSCL–T–HKGD16 PLSEATINGPLANEJTAMM0.25 (0.010)MMC14042B160MOTOROLA CMOS LOGIC DATAOUTLINE DIMENSIONSD SUFFIXPLASTIC SOIC PACKAGECASE 751B–05ISSUE J–A–NOTES:1.DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2.CONTROLLING DIMENSION: MILLIMETER.3.DIMENSIONS A AND B DO NOT INCLUDEMOLD PROTRUSION.4.MAXIMUM MOLD PROTRUSION 0.15 (0.006)PER SIDE.5.DIMENSION D DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.127 (0.005) TOTALIN EXCESS OF THE D DIMENSION ATMAXIMUM MATERIAL CONDITION.MILLIMETERSMINMAX9.8010.003.804.001.351.750.350.490.401.251.27 BSC0.190.250.100.250 7 __5.806.200.250.50INCHESMINMAX0.3860.3930.1500.1570.0540.0680.0140.0190.0160.0490.050 BSC0.0080.0090.0040.0090 7 __0.2290.2440.0100.019169–B–18P8 PL0.25 (0.010)MBSGFKC–T–SEATINGPLANERX 45_MD16 PLMJ0.25 (0.010)TBSASDIMABCDFGJKMPRHow to reach us:
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MOTOROLA CMOS LOGIC DATA
MC14042B
161