FPGA可编程逻辑器件芯片XC2V8000-6FF1152C中文规格书

Introduction to the RocketIO GTX Transceiver

Overview

The RocketIO™ GTX transceiver is a power-efficient transceiver for Virtex®-5 FPGAs. The GTX transceiver is highly configurable and tightly integrated with the programmable logic resources of the FPGA. It provides the following features to support a wide variety of applications:•••

Current Mode Logic (CML) serial drivers/buffers with configurable termination,voltage swing, and coupling.

Programmable TX pre-emphasis, RX equalization, and linear and decision feedbackequalization (DFE) for optimized signal integrity.

Line rates from 750Mb/s to 6.5Gb/s, with optional 5x digital oversampling requiredfor rates between 150Mb/s and 750Mb/s. The nominal operation range of the sharedPMA PLL is from 1.5GHz to 3.25GHz. These are nominal values, see DS202: Virtex-5FPGA Data Sheet for specifications.

Optional built-in PCS features, such as 8B/10B encoding, comma alignment, channelbonding, and clock correction.

Fixed latency modes for minimized, deterministic datapath latency.

Beacon signaling for PCI Express® designs and Out-of-Band signaling includingCOM signal support for SATA designs.

RX/TX Gearbox provides header insertion and extraction support for B/66B andB/67B (Interlaken) protocols.Receiver eye scan:

♦♦

•••••

Vertical eye scan in the voltage domain for testing purposesHorizontal eye scan in the time domain for testing purposes

The first-time user is recommended to read High-Speed Serial I/O Made Simple [Ref1], which discusses high-speed serial transceiver technology and its applications.

Table1-1 lists some of the standard protocols designers can implement using the GTX transceiver. The Xilinx® CORE Generator™ tool includes a Wizard to automatically configure GTX transceivers to support one of these protocols or perform custom configuration (see Chapter2, “RocketIO GTX Transceiver Wizard”).

The GTX_DUAL tile offers a data rate range and features that allow physical layer support for various protocols as illustrated in Table1-1.

RocketIO GTX Transceiver User GuideUG198 (v3.0) October 30, 2009

Ports and Attributes

Table 1-3:GTX_DUAL Port Summary (Cont’d)Port

DirIn

DomainRXUSRCLK2

Description

DFE tap 2 weight value control for each transceiver (4-bit resolution plus 1-bit sign).

Section (Page)Decision Feedback Equalization (page167)

DFETAP20[4:0]DFETAP21[4:0]

DFETAP2MONITOR0[4:0]DFETAP2MONITOR1[4:0]DFETAP30[3:0]DFETAP31[3:0]

DFETAP3MONITOR0[3:0]DFETAP3MONITOR1[3:0]DFETAP40[3:0]DFETAP41[3:0]

DFETAP4MONITOR0[3:0]DFETAP4MONITOR1[3:0]

OutRXUSRCLK2

DFE tap 2 weight value monitor

Decision Feedback

for each transceiver (4-bit

Equalization (page167)

resolution plus 1-bit sign).DFE tap 3 weight value control for each transceiver (3-bit resolution plus 1-bit sign).

Decision Feedback Equalization (page167)

InRXUSRCLK2

OutRXUSRCLK2

DFE tap 3 weight value monitor

Decision Feedback

for each transceiver (3-bit

Equalization (page167)

resolution plus 1-bit sign).DFE tap 4 weight value control for each transceiver (3-bit resolution plus 1-bit sign).

Decision Feedback Equalization (page167)

InRXUSRCLK2

OutRXUSRCLK2

DFE tap 4 weight value monitor

Decision Feedback

for each transceiver (3-bit

Equalization (page167)

resolution plus 1-bit sign).Data bus for writing

configuration data from the FPGA logic to the GTX_DUAL tile.

Data bus for reading

configuration data from the GTX_DUAL tile to the FPGA logic.

Dynamic Reconfiguration Port (page117)

DI[15:0]InDCLK

DO[15:0]OutDCLK

Dynamic Reconfiguration Port (page117)

DRDYOutDCLK

Indicates the operation is complete for DRP write

operations and data is valid for DRP read operations.Indicates whether the DRP operation is a read or a write.Starts the full GTX_DUAL reset sequence.

Factory test pins. Do not change default value.

Dynamic Reconfiguration Port (page117)

Dynamic Reconfiguration Port (page117)Reset (page102)

DWEGTXRESETGTXTEST[13:0]

InInIn

DCLKAsyncAsync

RocketIO GTX Transceiver User GuideUG198 (v3.0) October 30, 2009

Chapter 1:Introduction to the RocketIO GTX Transceiver

RocketIO GTX Transceiver User Guide

UG198 (v3.0) October 30, 2009

Chapter 4:Implementation

Table 4-1:GTX_DUAL Tile External Ports (Cont’d)Port

DirAnalogAnalogAnalog

DomainAnalogAnalogAnalog

Description

Two pads for 1.0V supply for transceiver mixed signal circuitryPad for 1.2V supply for RX circuitryTwo pads for 1.2V supply for TX circuitry

MGTAVCCMGTAVTTRXMGTAVTTTX

Notes:

1.These port names have the prefix MGT to identify them easily in a pad file that is often used to createsymbols for board design schematics. In this document, the MGT prefix was removed from thosenames; however, names with and without the MGT prefix are synonymous with each other.

There are no attributes for this section.

Description

The position of GTX_DUAL tiles is specified by an XY coordinate system that describes the column number and its relative position within that column. In current Virtex-5 FXT

devices, all GTX_DUAL tiles are located in a single column along one side of the die. TXT devices have one column of GTX_DUAL tiles on the right side of the die and one column of GTX_DUAL tiles on the left side of the device. As a result the X coordinate for all of the GTX_DUAL tiles is 0 on all FXT devices. On TXT devices, the left column is X0 and the right column is X1. “Package Placement Information,” page lists the GTX_DUAL tile position information for all available device and package combinations along with the pad numbers for the external signals associated with each tile. The Virtex-5 TXT devices have two columns of GTX_DUAL tiles. The left column on the die has the indices X0 and the right column of the die has the indices X1.

There are two ways to create a UCF for designs that utilize GTX_DUAL tiles. The preferred method is by using the RocketIO GTX Wizard (see Chapter2, “RocketIO GTX Transceiver Wizard”). The Wizard automatically generates UCF templates that configure the

transceivers and contain placeholders for GTX_DUAL placement information. The UCFs generated by the Wizard can then be edited to customize operating parameters and placement information for the application.

The second approach is to create the UCF by hand. When using this approach, the designer must enter both configuration attributes that control transceiver operation as well as tile location parameters. Care must be taken to ensure that all of the parameters needed to configure the GTX_DUAL tile are correctly entered.

RocketIO GTX Transceiver User Guide

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Package Placement Information

RocketIO GTX Transceiver User GuideUG198 (v3.0) October 30, 2009